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INTEGRATED CIRCUITS
PCA9564 Parallel bus to I2C-bus controller
Objective data 2003 Feb 26
Philips Semiconductors
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
DESCRIPTION
The PCA9564 is an integrated circuit designed in CMOS technology that serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus system to communicate bi-directionally with the I2C-bus. The PCA9564 can operate as a master or a slave and can be a transmitter or receiver. Communication with the I2C-bus is carried out on a byte-wise basis using interrupt or polled handshake. The PCA9564 controls all the I2C-bus specific sequences, protocol, arbitration and timing with no external timing element required.
FEATURES
* Parallel-bus to I2C-bus protocol converter and interface * Both master and slave functions * Multi-master capability * Internal oscillator * Operating supply voltage 2.3 V to 3.6 V * 5 V tolerant I/Os * Standard and fast mode I2C capable and compatible with SMBus * ESD protection exceeds 2000 V HEM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
The PCA9564 is similar to the PCF8584 but operates at lower voltages and higher I@C frequencies. Other enhancements requested by design engineers have also been incorporated into this device. Characteristic Voltage range Maximum I2C frequency Clock source PCA9564 2.3-3.6 V 360 kHz Internal PCF8584 4.5-5.5 V 90 kHz External Comments PCA9564 is 5 V tolerant Faster I2C interface Less expensive and more flexible with oscillator regulated to within 10% Compatible with faster processors
* Latch-up testing is done to JEDEC Standard JESD78 which
exceed 100 mA.
* Packages offered: SO20, TSSOP20, HVQFN20
Parallel interface
Fast
Slow
The maximum I2C frequency for the PCF8584 is 90 kHz if you stay with one of the standard input clock frequencies (3.0, 4.43, 6.0, 8.0, or 12.0 MHz) -- see Tables 2 and 3 in the PCF8584 spec. It is recommended that you use one of these input frequencies. This clock should be a 50% (5%) duty cycle. The PCF8584 can be used in slave mode at 100 kHz. While the PCF8584 supported most parallel-bus microcontrollers/ microprocessors including the Intel 8049/8051, Motorola 6800/68000 and the Xicor Z80, the PCA9564 has been designed to be very similar to the Philips standard 80C51 microcontroller I2C hardware so existing code can be utilized with a few modifications. This feature limits the PCA9564 to use with the Intel 8051 architecture. The PCA9564 also does not support bus monitor "Snoop" mode.
ORDERING INFORMATION
PACKAGES 20-Pin Plastic SO 20-Pin Plastic TSSOP 20-Pin Plastic HVQFN TEMPERATURE RANGE -40 to +85 C -40 to +85 C -40 to +85 C ORDER CODE PCA9564D PCA9564PW PCA9564BS DRAWING NUMBER SOT163-1 SOT360-1 SOT662-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
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Objective data
Parallel bus to I2C-bus controller
PCA9564
PIN CONFIGURATION -- SO, TSSOP
PIN CONFIGURATION -- HVQFN
D2 20 D1 19 D0 VDD SDA 18 17 16 15
D0 D1 D2 D3 D4 D5 D6 D7 NC
1 2 3 4 5 6 7 8 9
20 VDD 19 SDA 18 SCL 17 RESET 16 INT 15 A1 14 A0 13 CE 12 RD 11 WR su01485 D3 D4 D5 D6 D7 1 2 3 4 5
SCL
14 RESET 13 INT 12 A1 11 A0 10 6 7 8 9
NC GND WR (VSS)
RD CE
VSS 10
TOP VIEW
su01665
PIN CONFIGURATION
PIN NUMBER SO, TSSOP 1, 2, 3, 4, 5, 6, 7, 8 9 10 11 12 13 HVQFN 1, 2, 3, 4, 5, 18, 19, 20 6 7 8 9 10 SYMBOL D0-D7 PIN TYPE I/O NAME AND FUNCTION Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the controller and the CPU. D0 is the least significant bit. No connect: must be left floating Pwr I I I Ground Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RD. Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the controller are enabled on D0-D7 as controlled by the WR, RD and A0-A1 inputs. When HIGH, places the D0-D7 lines in the 3-State condition. Address Inputs: Selects the controller internal registers and ports for read/write operations. Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device. Reset: A LOW level clears internal registers resets the I2C state machine. I2C-bus serial clock input/output (open-drain). I2C-bus serial data input/output (open-drain). Power Supply: +2.3 to +3.6 V
NC VSS WR RD CE
14, 15 16 17 18 19 20
11, 12 13 14 15 16 17
A0, A1 INT RESET SCL SDA VDD
I O I I/O I/O Pwr
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Objective data
Parallel bus to I2C-bus controller
PCA9564
PCA9564
8 D0-D7 BUS BUFFER
RD WR CE A0 A1 RESET
OPERATION CONTROL ADDRESS DECODE R/W CONTROL SCL
VDD
POWER-ON RESET
MASTER/SLAVE STATE MACHINES
INPUT FILTER
SDA INT INTERRUPT CONTROL INTERNAL DATABUS
CONTROL
TIMING
CLOCK SELECTORS
INTERNAL OSCILLATOR
TIMING
VSS
SD00707
Figure 1. Block diagram
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Objective data
Parallel bus to I2C-bus controller
PCA9564
FUNCTIONAL DESCRIPTION General
The PCA9564 acts as an interface device between standard high-speed parallel buses and the serial I2C-bus. On the I2C-bus, it can act either as master or slave. Bidirectional data transfer between the I2C-bus and the parallel-bus microcontroller is carried out on a byte-wise basis, using either an interrupt or polled handshake.
The Address Register, I2CADR: I2CADR is not affected by the SIO hardware. The contents of this register are irrelevant when SIO is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontroller's own slave address.
7 I2CADR BIT7 6 BIT6 5 BIT5 4 BIT4 3 BIT3 2 BIT2 1 BIT1 0 0
own slave address
Internal Oscillator
The PCA9564 contains an internal 9 MHz oscillator which is used for all I2C and parallel bus timing. The oscillator has a variance of 10% over the entire temperature range. The oscillator requires 500 s to start-up.
The most significant bit corresponds to the first bit received from the I2C-bus after a start condition. A logic 1 in I2CADR corresponds to a HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW level on the bus. The least significant bit is not used but should be programmed with a `0'. The Data Register, I2CDAT: I2CDAT contains a byte of serial data to be transmitted or a byte which has just been received. In master mode, this includes the slave address that the master wants to send out on the I2C-bus, with the most significant bit of the slave address in the SD7 bit position and the Read/Write bit in the SD0 bit position. The CPU can read from and write to this 8-bit register while it is not in the process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the SIO generates an interrupt, the I2CDAT registers contain the data byte that was just transferred on the I2C-bus.
7 I2CDAT SD7 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0
Registers
The PCA9564 contains four registers which are used to configure the operation of the device as well as to send and receive serial data. The registers are selected by setting pins A0 and A1 to the appropriate logic levels before a read or write operation is executed. CAUTION: Do not write to I2C registers while the I2C-bus is busy and the SIO is in master or addressed slave mode. REGISTER NAME I2CSTA I2CTO I2CDAT I2CADR I2CCON REGISTER FUNCTION Status Time-out Data Own address Control A1 0 0 0 1 1 A0 0 0 1 0 1 READ/ WRITE R W R/W R/W R/W DEFAULT F8h FFh 00h 00h 00H
* SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to a HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW level on the bus. The Control Register, I2CCON: The microcontroller can read from and write to this 8-bit register. Two bits are affected by the SIO hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C-bus.
7 I2CCON AA 6 ENSIO 5 STA 4 STO 3 SI 2 CR2 1 CR1 0 CR0
The Time-out Register, I2CTO: The time-out register is used to determine the maximum time that SCL is allowed to be LOW before the I2C state machine is reset. When the I2C interface is operating, I2CTO is loaded in the time-out counter at every SCL transition.
7 I2CTO TE 6 TO6 5 TO5 4 TO4 3 TO3 2 TO2 1 TO1 0 TO0
Time-out value
* ENSIO, THE SIO ENABLE BIT
ENSIO = "0": When ENSIO is "0", the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO is in the "not addressed" slave state. ENSIO = "1": When ENSIO is "1", SIO is enabled. After the ENSIO bit is set, it takes 500 s for the internal oscillator to start up, therefore, the PCA9564 will enter either the master or the slave mode after this time. ENSIO should not be used to temporarily release the PCA9564 from the I2C-bus since, when ENSIO is reset, the I2C-bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). In the following text, it is assumed that ENSIO = "1".
The most significant bit of I2CTO (TE) is used as a time-out enable/disable. A "1" will enable the time-out function. The time-out period = (I2CTO[6:0] x 113.7 s). The time-out value has a variance of 10% over the entire temperature range. The time-out register can be used in the following cases: 1. When the SIO, in the master mode, wants to send a START condition and the SCL line is held LOW by some other device. The SIO waits a time period equivalent to the time-out value for the SCL to be released. In case it is not released, the SIO concludes that there is a bus error, loads 90H in the I2CSTA register, generates an interrupt signal and releases the SCL and SDA lines. After the microcontroller reads the status register, it needs to send an external reset signal in order to reset the SIO. 2. In the master mode, the time-out feature starts every time the SCL goes LOW. If SCL stays LOW for a time period equal to or greater than the time-out value, the SIO concludes there is a bus error and behaves in the manner described above. 3. In case of a forced access to the I2C-bus. (See more details on page 15.)
* STA, THE START FLAG
STA = "1": When the STA bit is set to enter a master mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free. If the bus is not free, then SIO waits for a STOP condition (which will free the bus) and generates a START condition after the minimum buffer time (tBUF) has elapsed.
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Objective data
Parallel bus to I2C-bus controller
PCA9564
If STA is set while SIO is already in a master mode and one or more bytes are transmitted or received, SIO transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO is an addressed slave. STA = "0": When the STA bit is reset, no START condition or repeated START condition will be generated.
* THE CLOCK RATE BITS, CR2, CR1, AND CR0
Three bits determine the serial clock frequency when SIO is in master mode. The various serial rates are shown in Table 1. The clock frequencies only take the HIGH and LOW times into consideration. The rise and fall time will cause the actual measured frequency to be lower than expected. The frequencies shown in Table 1 are unimportant when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize with any clock frequency up to 400 kHz.
* STO, THE STOP FLAG
STO = "1": When the STO bit is set while SIO is in a master mode, a STOP condition is transmitted to the I2C-bus. When the STOP condition is detected on the bus, the SIO hardware clears the STO flag. If the STA and STO bits are both set, then a STOP condition is transmitted to the I2C-bus if SIO is in a master mode. SIO then transmits a START condition. STO = "0": When the STO bit is reset, no STOP condition will be generated.
Table 1. Serial Clock Rates
CR2 CR1 CR0 SERIAL CLOCK FREQUENCY (kHz)
* SI, THE SERIAL INTERRUPT FLAG
SI = "1": When the SI flag is set, then, if the ENSIO bit is also set, a serial interrupt is requested. SI is set by hardware when one of 24 of the 25 possible SIO states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the LOW period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A HIGH level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software. The SI bit should never be set by the user. SI = "0": When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line.
0 0 0 330 0 0 1 288 0 1 0 217 0 1 1 146 1 0 0 88 1 0 1 59 1 1 0 44 1 1 1 36 NOTE: The clock frequency values have a 10% variance over the entire temperature range. The Status Register, I2CSTA: I2CSTA is an 8-bit read-only register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 25 possible status codes. When I2CSTA contains F8H, no relevant state information is available and no serial interrupt is requested. All other I2CSTA values correspond to defined SIO states. When each of these states is entered, a serial interrupt is requested (SI = "1").
* AA, THE ASSERT ACKNOWLEDGE FLAG
AA = "1": If the AA flag is set, an acknowledge (LOW level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: - The "own slave address" has been received - A data byte has been received while SIO is in the master receiver mode - A data byte has been received while SIO is in the addressed slave receiver mode AA = "0": if the AA flag is reset, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock pulse on SCL when: - A data has been received while SIO is in the master receiver mode - A data byte has been received while SIO is in the addressed slave receiver mode - "Own slave address" has been received When SIO is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 5). When SI is cleared, enters the not addressed slave receiver mode, and the SDA line remains at a HIGH level. In state C8H, the AA flag can be set again for future address recognition. When SIO is in the not addressed slave mode, its own slave address is ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO can be temporarily released from the I2C-bus while the bus status is monitored. While SIO is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag.
More Information on SIO Operating Modes
The four operating modes are: - Master Transmitter - Master Receiver - Slave Receiver - Slave Transmitter Data transfers in each mode of operation are shown in Figures 2-5. These figures contain the following abbreviations: Abbreviation S SLA R W A A Data P Explanation Start condition 7-bit slave address Read bit (HIGH level at SDA) Write bit (LOW level at SDA) Acknowledge bit (LOW level at SDA) Not acknowledge bit (HIGH level at SDA) 8-bit data byte Stop condition
In Figures 2-5, circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not generated when I2CSTA = F8H. This happens on a stop condition. The numbers in the circles show the status code held in the I2CSTA register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to the appropriate service routine. For each status
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Objective data
Parallel bus to I2C-bus controller
PCA9564
code, the required software action and details of the following serial transfer are given in Tables 2-6. Master Transmitter Mode: In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 2). Before the master transmitter mode can be entered, I2CCON must be initialized as follows:
7 I2CCON AA X 6 ENSIO 1 5 STA 0 4 STO 0 3 SI 0 2 CR2 1 CR1 bit rate 0 CR0
I2CSTA are possible. These are 40H, 48H, or 38H for the master mode and also 68H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 3. ENSIO is not affected by the serial transfer and are not referred to in Table 3. After a repeated start condition (state 10H), SIO may switch to the master transmitter mode by loading I2CDAT with SLA+W. Note that a master should not transmit its own slave address. Slave Receiver Mode: In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 4). To initiate the slave receiver mode, I2CADR and I2CCON must be loaded as follows:
7 I2CADR BIT7 6 BIT6 5 BIT5 4 BIT4 3 BIT3 2 BIT2 1 BIT1 0 0
ENSIO must be set to logic 1 to enable SIO. If the AA bit is reset, SIO will not acknowledge its own slave address in the event of another device becoming master of the bus. In other words, if AA is reset, SIO cannot enter a slave mode. STA, STO, and SI must be reset. The master transmitter mode may now be entered by setting the STA bit. The SIO logic will now test the I2C-bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (I2CSTA) will be 08H. This status code must be used to vector to an interrupt service routine that loads I2CDAT with the slave address and the data direction bit (SLA+W). The SI bit in I2CCON must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in I2CSTA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 2. After a repeated start condition (state 10H). SIO may switch to the master receiver mode by loading I2CDAT with SLA+R). Note that a master should never transmit its own slave address. Master Receiver Mode: In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 3). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load I2CDAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CCON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in
own slave address
The upper 7 bits are the address to which SIO will respond when addressed by a master.
7 I2CCON AA 1 6 ENSIO 1 5 STA 0 4 STO 0 3 SI 0 2 CR2 X 1 CR1 X 0 CR0 X
ENSIO must be set to logic 1 to enable SIO. The AA bit must be set to enable SIO to acknowledge its own slave address, STA, STO, and SI must be reset. When I2CADR and I2CCON have been initialized, SIO waits until it is addressed by its own slave address followed by the data direction bit which must be "0" (W) for SIO to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from I2CSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 4. The slave receiver mode may also be entered if arbitration is lost while SIO is in the master mode (see status 68H). If the AA bit is reset during a transfer, SIO will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SIO does not respond to its own slave address. However, the I2C-bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO from the I2C-bus.
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Objective data
Parallel bus to I2C-bus controller
PCA9564
MT
SUCCESSFUL TRANSMISSION TO A SLAVE RECEIVER
NEXT TRANSFER STARTED WITH A REPEATED START CONDITION
NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS
A
P
20H
F8H
NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE
A
30H
ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE
A or A
OTHER MST CONTINUES
A or A
38H
38H
ARBITRATION LOST AND ADDRESSED AS SLAVE
A
OTHER MST CONTINUES
68H
TO CORRESPONDING STATES IN SLAVE RECEIVER MODE TO CORRESPONDING STATES IN SLAVE TRANSMITTER MODE
FROM MASTER TO SLAVE
B0H
FROM SLAVE TO MASTER
Data
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 2.
NOTE: THE MASTER SHOULD NEVER TRANSMIT ITS OWN SLAVE ADDRESS
Figure 2. Format and states in the master transmitter mode
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CCC CCC CCC CCC CCC CCCCCCC CCCCCCC CCCCCCC
S SLA W 10H R P F8H OTHER MST CONTINUES SW00816
CCC CCC C CCC CCCCC CCCCCCCC CCC CCCCCCCC
S SLA W A DATA A P 08H 18H 28H F8
CCC CCC
TO MST/REC MODE ENTRY = MR
CC C CCCC C CCCC CCCC CCC CCCC CCCC CCCC
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
MR
SUCCESSFUL RECEPTION FROM A SLAVE TRANSMITTER
S
SLA
R
A
DATA
08H
40H
NEXT TRANSFER STARTED WITH A REPEATED START CONDITION
NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS
A
P
48H
F8H
ARBITRATION LOST IN SLAVE ADDRESS OR ACKNOWLEDGE BIT
A or A
OTHER MST CONTINUES
A
38H
38H
ARBITRATION LOST AND ADDRESSED AS SLAVE
A
OTHER MST CONTINUES
68H
TO CORRESPONDING STATES IN SLAVE RECEIVER MODE TO CORRESPONDING STATES IN SLAVE TRANSMITTER MODE
B0H
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
DATA
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 3.
Figure 3. Format and states in the master receiver mode
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CCC CCC CCCCCCC CCCCCCC CCCCCCC
S SLA R 10H W TO MST/TRX MODE ENTRY = MT
CCC C C C CCCCCCCCCC CCCCCCCC CC
A DATA A P 50H 58H F8H
CCC CCC CCC
CCC CCC
CCCCCCCC CCCCCCCC
OTHER MST CONTINUES
CC CCCCC C CCCC CCCC CCCC
SW00817
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
RECEPTION OF THE OWN SLAVE ADDRESS AND ONE OR MORE DATA BYTES ALL ARE ACKNOWLEDGED.
LAST DATA BYTE RECEIVED IS NOT ACKNOWLEDGED
ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Data
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 4. SW00814
RECEPTION OF THE OWN SLAVE ADDRESS AND TRANSMISSION OF ONE OR MORE DATA BYTES
S
SLA
ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE
FROM MASTER TO SLAVE
B0H
LAST DATA BYTE TRANSMITTED. SWITCHED TO NOT ADDRESSED SLAVE (AA BIT IN I2CCON = "0")
A
All "1"s
FROM SLAVE TO MASTER
C8H
DATA
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 5. SW00815
Figure 5. Format and states of the slave transmitter mode
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CCC CCC CCC
CCC CCC CCC CCC CCCCCCCC C CCC CCCCCCCCCC CCCCCCC CCC CCCCCCC
S SLA W A DATA A DATA SLA A P or S 60H 80H 80H A0H A P or S 88H F8H ON STOP A
Figure 4. Format and states in the slave receiver mode
R
A
DATA
A8H
A
CCCCCCCCCC CC C CCC C C C CCCCCCCCCC CCCCCCCC CC
CCC CCC CCC
CCC CCC CCC
P or S F8 A B8H
68H
CCCCCCCC CCCCCCCC CCCCCCCC
CC CC CCCCC C CCCC CCCC CCCC CCCC CCCC
CC C CCCC CCCC CCC CCCC CCCC CCCC CCCC
ON STOP
DATA
A
P or S
C0H
F8H
ON STOP
P or S
F8H
ON STOP
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
Table 2.
STATUS CODE (I2CSTA) 08H 10H
Master Transmitter Mode
STATUS OF THE I2C BUS AND SIO HARDWARE A START condition has been transmitted A repeated START condition has been transmitted SLA+W has been transmitted; ACK has been received APPLICATION SOFTWARE RESPONSE TO I2CCON TO/FROM I2CDAT Load SLA+W Load SLA+W or Load SLA+R Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action STA X X X 0 1 0 1 STO X X X 0 0 1 1 SI 0 0 0 0 0 0 0 AA X X X X X X X SLA+W will be transmitted; ACK bit will be received As above SLA+R will be transmitted; SIO will be switched to MST/REC mode Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset I2C-bus will be released; not addressed slave will be entered A START condition will be transmitted when the bus becomes free NEXT ACTION TAKEN BY SIO HARDWARE
18H
20H
SLA+W has been transmitted; NOT ACK has been received
Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
28H
Data byte in I2CDAT has been transmitted; ACK has been received
Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
30H
Data byte in I2CDAT has been transmitted; NOT ACK has been received
Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
38H
Arbitration lost in SLA+W or Data bytes
No I2CDAT action or No I2CDAT action
0 1
0 0
0 0
X X
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Objective data
Parallel bus to I2C-bus controller
PCA9564
Table 3.
STATUS CODE (I2CSTA) 08H 10H
Master Receiver Mode
STATUS OF THE I2C BUS AND SIO HARDWARE A START condition has been transmitted A repeated START condition has been transmitted Arbitration lost in NOT ACK bit APPLICATION SOFTWARE RESPONSE TO I2CCON TO/FROM I2CDAT Load SLA+R Load SLA+R or Load SLA+W No I2CDAT action or No I2CDAT action STA X X X 0 1 0 0 1 0 1 STO X X X 0 0 0 0 0 1 1 SI 0 0 0 0 0 0 0 0 0 0 AA X X X X X 0 1 X X X SLA+R will be transmitted; ACK bit will be received As above SLA+W will be transmitted; SIO will be switched to MST/TRX mode I2C-bus will be released; SIO will enter a slave mode A START condition will be transmitted when the bus becomes free Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset I2C-bus will be released; not addressed slave will be entered A START condition will be transmitted when the bus becomes free NEXT ACTION TAKEN BY SIO HARDWARE
38H
40H
SLA+R has been transmitted; ACK has been received SLA+R has been transmitted; NOT ACK has been received
No I2CDAT action or no I2CDAT action No I2CDAT action or no I2CDAT action or no I2CDAT action
48H
50H
Data byte has been received; ACK has been returned Data byte has been received; NOT ACK has been returned
Read data byte or read data byte Read data byte or read data byte or read data byte
0 0 1 0 1
0 0 0 1 1
0 0 0 0 0
0 1 X X X
58H
38H
Arbitration lost in SLA+R
No I2CDAT action or No I2CDAT action
0 1
0 0
0 0
X X
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
Table 4.
STATUS CODE (I2CSTA) 60H
Slave Receiver Mode
STATUS OF THE I2C BUS AND SIO HARDWARE Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; Own SLA+W has been received, ACK returned Previously addressed with own SLV address; DATA has been received; ACK has been returned Previously addressed with own SLA; DATA byte has been received; NOT ACK has been returned APPLICATION SOFTWARE RESPONSE TO I2CCON TO/FROM I2CDAT No I2CDAT action or no I2CDAT action No I2CDAT action or no I2CDAT action Read data byte or STA X X X STO X X X SI 0 0 0 AA 0 1 0 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO HARDWARE
68H
X X
X X
0 0
1 0
80H
read data byte Read data byte or read data byte or read data byte or
X 0 0 1
X X X X
0 0 0 0
1 0 1 0
88H
read data byte
1
X
0
1
A0H
A STOP condition or repeated START condition has been received while still addressed as SLV/REC
No I2CDAT action or No I2CDAT action or No I2CDAT action or No I2CDAT action
0 0 1
X X X
0 0 0
0 1 0
1
X
0
1
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
Table 5.
STATUS CODE (I2CSTA) A8H
Slave Transmitter Mode
STATUS OF THE I2C BUS AND SIO HARDWARE Own SLA+R has been received; ACK has been returned Arbitration lost in SLA+R/W as master; Own SLA+R has been received, ACK has been returned Data byte in I2CDAT has been transmitted; ACK has been received Data byte in I2CDAT has been transmitted; NOT ACK has been received APPLICATION SOFTWARE RESPONSE TO I2CCON TO/FROM I2CDAT Load data byte or load data byte Load data byte or load data byte Load data byte or load data byte No I2CDAT action or no I2CDAT action or no I2CDAT action or STA X X X X X X 0 0 1 STO X X X X X X X X X SI 0 0 0 0 0 0 0 0 0 AA 0 1 0 1 0 1 0 1 0 Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. Switched to not addressed SLV mode; no recognition of own SLA Switched to not addressed SLV mode; Own SLA will be recognized Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO HARDWARE
B0H
B8H
C0H
no I2CDAT action
1
X
0
1
C8H
Last data byte in I2CDAT has been transmitted (AA = 0); ACK has been received
No I2CDAT action or no I2CDAT action or no I2CDAT action or
0 0 1
X X X
0 0 0
0 1 0
no I2CDAT action
1
X
0
1
Table 6.
STATUS CODE (I2CSTA) F8H
Miscellaneous States
STATUS OF THE I2C BUS AND SIO HARDWARE On reset or STOP APPLICATION SOFTWARE RESPONSE TO I2CCON TO/FROM I2CDAT No I2CDAT action No I2CDAT action No I2CDAT action STA 1 0 0 STO X X X SI 0 0 0 AA X 0 1 Go into master mode; send START No recognition of own SLA Will recognize own SLA Reset SIO Reset SIO Reset SIO NEXT ACTION TAKEN BY SIO HARDWARE
70H 90H 00H
Bus error SDA stuck LOW Bus error SCL stuck LOW Bus error during master or slave mode, due to illegal START or STOP condition
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
Slave Transmitter Mode: In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 5). Data transfer is initialized as in the slave receiver mode. When I2CADR and I2CCON have been initialized, SIO waits until it is addressed by its own slave address followed by the data direction bit which must be "1" (R) for SIO to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from I2CSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 5. The slave transmitter mode may also be entered if arbitration is lost while SIO is in the master mode (see state B0H). If the AA bit is reset during a transfer, SIO will transmit the last byte of the transfer and enter state C8H. SIO is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, SIO does not respond to its own slave address. However, the I2C-bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO from the I2C-bus. Miscellaneous States: There are four I2CSTA codes that do not correspond to a defined SIO hardware state (see Table 6). These are discussed below. I2CSTA = F8H: This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs on a STOP condition and when SIO is not involved in a serial transfer. I2CSTA = 00H: This status code indicates that a bus error has occurred during an SIO serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal SIO signals. When a bus error occurs, SI is set. To recover from a bus error, the microcontroller must send an external reset signal to reset the SIO.
I2CSTA = 70H: This status code indicates that the SDA line is stuck LOW when the SIO, in master mode, is trying to send a START condition. I2CSTA = 90H: This status code indicates that the SCL line is stuck LOW. Some Special Cases: The SIO hardware has facilities to handle the following special cases that may occur during a serial transfer:
* SIMULTANEOUS REPEATED START CONDITIONS FROM TWO MASTERS
A repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a repeated START condition (see Figure 6). Until this occurs, arbitration is not lost by either master since they were both transmitting the same data.
If the SIO hardware detects a repeated START condition on the I2C-bus before generating a repeated START condition itself, it will use the repeated START as its own and continue with the sending of the slave address.
* DATA TRANSFER AFTER LOSS OF ARBITRATION
Arbitration may be lost in the master transmitter and master receiver modes. Loss of arbitration is indicated by the following states in I2CSTA; 38H, 68H, and B0H (see Figures 2 and 3). If the STA flag in I2CCON is set by the routines which service these states, then, if the bus is free again, a START condition (state 08H) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence.
* FORCED ACCESS TO THE I2C BUS
In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I2C-bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I2C-bus is possible. If the I2C-bus stays idle for a time period equal to the time out period, then the '64 concludes that no other master is using the bus and sends a START condition.
S
SLA
W
A
DATA
A
S
BOTH MASTERS CONTINUE WITH SLA TRANSMISSION
08H
18H
28H
OTHER MASTER SENDS REPEATED START CONDITION EARLIER SU00975
Figure 6. Simultaneous repeated START conditions from 2 masters
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
TIME OUT
STA FLAG
SDA LINE
SCL LINE
START CONDITION
SU00976
Figure 7. Forced access to a busy I2C-bus
* I2C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA
hang-up occurs if SDA or SCL is pulled LOW by an An uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the SIO hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW. When the SCL line stays LOW for a period equal to the time-out value, the '64 concludes that these is a bus error and behaves in a manner described on page 5 under "Time-out Register". If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the SCL line (see Figure 8). The SIO hardware sends out nine clock pulses followed by the STOP condition. If the SDA line is released by the slave pulling it LOW, a normal START condition is transmitted by the SIO, state 08H is entered and the serial transfer continues. If the SDA line is not released by the slave pulling it LOW, then the SIO concludes that there is a bus error, loads 70H in I2CSTA, generates an interrupt signal, and releases the SCL and SDA lines. After the I2C-bus
microcontroller reads the status register, it needs to send an external reset signal in order to reset the SIO. If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the SIO hardware performs the same action as described above. In each case, state 08H is entered after a successful START condition is transmitted and normal serial transfer continues. Note that the CPU is not involved in solving these bus hang-up problems.
* BUS ERROR
A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. The SIO hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, SIO releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 6. The microcontroller must send an external reset signal to reset the SIO.
STA FLAG
SDA LINE
1 SCL LINE
2
3
4
5
6
7
8
9
STOP CONDITION
START CONDITION su01663
Figure 8. Recovering from a bus obstruction caused by a LOW level on SDA
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
I2C-BUS TIMING DIAGRAMS
The diagrams (Figures 9 to 12) illustrate typical timing diagrams for the PCA9564 in master/slave functions.
SCL
SDA
INT
7-bit address R/W = 0 START condition from slave receiver Master PCA9564 writes data to slave transmitter. ACK
interrupt
first-byte ACK
interrupt
nbyte ACK
interrupt STOP condition
su01490
Figure 9. Bus timing diagram; master transmitter mode
SCL
SDA
INT
7-bit address R/W = 1 START condition ACK
interrupt
first-byte ACK
interrupt
nbyte no ACK STOP condition
from slave Master PCA9564 reads data from slave transmitter.
from master receiver su01491
Figure 10. Bus timing diagram; master receiver mode
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
SCL
SDA
INT
7-bit address R/W = 1 START condition ACK
interrupt
first-byte ACK
interrupt
nbyte no ACK
interrupt STOP condition
from slave PCA9564
from master receiver su14092
External master receiver reads data from PCA9564.
Figure 11. Bus timing diagram; slave transmitter mode
SCL
SDA
INT
7-bit address R/W = 0 START condition ACK
interrupt
first-byte ACK
interrupt
nbyte ACK
interrupt
interrupt (after STOP) STOP condition
from slave PCA9564
Slave PCA9564 is written to by external master transmitter.
su01493
Figure 12. Bus timing diagram; slave receiver mode
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
VDD
ADDRESS BUS
VDD VDD A0 A1
DECODER ALE
PCA9564
CE SCL 8 D[0:7] RD WR VDD SDA
SLAVE INT RESET
80C51
INT RESET VSS VDD
VSS
SD00705
Figure 13. Application diagram using the 80C51
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI II IO Ptot PO Tamb Tstg Supply voltage Voltage range (any input) DC input current (any input) DC output current (any output) Total power dissipation Power dissipation per output Operating ambient temperature Storage temperature PARAMETER CONDITIONS MIN -0.3 -0.8 -10 -10 -- -- -40 -65 MAX +4.6 -- +10 +10 300 50 +85 +150 UNIT V V mA mA mW mW C C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".
DC CHARACTERISTICS
VDD = 2.3 V to 3.6 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD IDD VPOR VIL VIH CI VIL VIH IOL CIO Outputs INT IOH IOL IOL CO HIGH level output current LOW level output current Leakage current Output capacitance VOH = 2.4 V VOL = 0.4 V -2.4 3.0 -1 -- -- -- -- -- +1 mA mA A pF Supply voltage Supply current Power-on Reset voltage LOW level input voltage HIGH level input voltage Input capacitance LOW level input voltage HIGH level input voltage LOW level output current Input/output capacitance VOL = 0.4 V 0 0.7 VDD 3.0 -- -- -- 0.3 VDD 5.5 -- standby operating 2.3 -- -- -- 0 2.0 -- -- -- 1.8 -- -- 3.6 -- -- -- 0.8 VDD V A mA V V V pF V V mA pF PARAMETER CONDITIONS MIN TYP MAX UNIT
Inputs WR, RD, A0, A1, CE, RESET, D0 to D7
SDA and SCL
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
SDA
tF
tLOW
tR
tSU;DAT
tF
tHD;STA
tSP
tR
tBUF
SCL
S
tHD;STA
tHD;DAT tHIGH
tSU;STA
SR
tSU;STD
P
S
SU01469
Figure 14. Definition of timing
I2C-BUS TIMING SPECIFICATIONS
All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 3.3 V 10%, Tamb = -40 to +85 C; and refer to VIL and VIH with an input voltage of VSS to VDD. SYMBOL fSCL tSW tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP Operating frequency Tolerable spike width on bus Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK condition Data out valid time Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters PARAMETER STANDARD MODE I2C BUS MIN 0 -- 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -- -- -- MAX 100 50 -- -- -- -- -- 3.45 -- -- -- -- 300 1000 50 FAST MODE I2C BUS MIN 0 -- 1.3 0.6 0.6 0.6 0 0.1 -- 100 1.3 0.6 -- -- -- MAX 400 50 -- -- -- -- -- 0.9 0.9 -- -- -- 1.0 0.3 50 kHz ns s s s s ns s s ns s s s s ns UNITS
RESET
tRES SD00712
Figure 15. Reset timing
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
A0-A1
tAS tAH CE tCS tRW RD tCH tRWD
tDD D0-D7 (READ) NOT VALID
tDF
FLOAT
VALID
FLOAT
tRWD WR
tDS tDH D0-D7 (WRITE) VALID SD00711
Figure 16. Bus timing
AC CHARACTERISTICS (3.3 VOLT) 1, 2, 3
AAAA A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
LIMITS SYMBOL tRES tAS PARAMETER Min 100 0 0 0 Max -- -- -- -- -- -- UNIT ns ns ns ns ns ns ns ns ns ns ns Reset Timing (See Figure 8) Bus Timing (See Figure 16) tAH Reset pulse width A0-A1 setup time to RD, WR LOW CE setup time to RD, WR LOW WR, RD pulse width (Low time) Data valid after RD LOW A0-A1 hold time from RD, WR LOW CE Hold time from RD, WR LOW 10 tCS tCH tDD tDF tDS tRW 15 -- -- 0 15 15 -- -- -- Data bus floating after RD or CE HIGH Data hold time after WR HIGH Data bus setup time before WR or CE HIGH (write cycle) High time between read and/or write cycles 10 15 tDH tRWD NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. 3. Test conditions for outputs: CL = 80 pF, except open drain outputs. Test conditions for open drain outputs: CL = 80 pF, constant current source = 2.6 mA. 2003 Feb 26 22
VCC = 3.3 V 10%, Tamb = -40 to +85 C, unless otherwise specified. (See page 23 for 2.5 V.)
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
AC CHARACTERISTICS (2.5 VOLT) 1, 2, 3
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAA A AAAA A A A A A A A A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAA A A AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
LIMITS SYMBOL tRES tAS PARAMETER Min 100 0 5 0 0 Max -- -- -- -- -- -- 5 UNIT ns ns ns ns ns ns ns ns ns ns ns Reset Timing (See Figure 8) Bus Timing (See Figure 16) tAH Reset pulse width A0-A1 setup time to RD, WR LOW CE setup time to RD, WR LOW WR, RD pulse width (low time) A0-A hold time from RD, WR LOW CE Hold time from RD, WR LOW tCS tCH tDD tDF tDS tRW 20 -- -- 0 Data valid after RD LOW (125 pF load.) Data bus floating after RD or CE HIGH Data hold time after WR HIGH 10 -- -- -- Data bus setup time before WR or CE HIGH (write cycle) High time between read and/or write cycles 10 12 tDH tRWD NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of 5 ns maximum. All time measurements are referenced at input voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. 3. Test conditions for outputs: CL = 80 pF, except open drain outputs. Test conditions for open drain outputs: CL = 80 pF, constant current source = 2.6 mA. 2003 Feb 26 23
VCC = 2.5 V 10%, Tamb = -40 to +85 C, unless otherwise specified. (See page 22 for 3.3 V.)
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
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Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
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25
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
HVQFN20: plastic, heatsink very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm
SOT662-1
2003 Feb 26
26
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
REVISION HISTORY Rev Date _1 20030226
Description Objective data (9397 750 11153)
2003 Feb 26
27
Philips Semiconductors
Objective data
Parallel bus to I2C-bus controller
PCA9564
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status[1]
Objective data
Product status[2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 02-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11153
Philips Semiconductors
2003 Feb 26 28

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